Precision swept oscillator



Jan. 16, 1968 PRECI S ION SWEPT OSCILLATOR Filed Dec. 9, 1966 2Sheets-Sheet 1 swEEP VOLTAGE CONTROLLED FRSEIEIEJJEECY OSCILLATOR OUTPUTl7 DIVIDER DIVIDE NETwOR RATIO K sELEcTOR I5 l4 REFERENCE PHASEFREQUENCY T GENERATOR l6 COMPARA 0R T3 FlG Lu I) 9 3 E o FREQUENCY CURVEl9 SWEEPING INTERVAL L I FLYBACKT INTERVAL TIME FIG 2 THOMAS L. LOPOSERGORDON D. MCKINLEY AGENT Jan. 16, 1968 T. L. LOPOSER ET AL 3,364,437

PRECI S ION SWEPT OSCILLATOR Filed Dec. 9, 1966 2 Sheets-Sheet 2vARIABLE SWEEP FREQUENCY FREQUENCY CONTROL SIGNAL OSCILLATOR OUTPUT l6 vIA PHASE 4 RATIO COMPARATOR B FREQUENCY OIvIOER '5 (COUNTER) 54REFERENCE 23 SWEEP FREQUENCY SIGNAL WRITE RATE GENERATOR 24 MATRIXSELECTOR I 22 33 PROGRAM SWEEP FREQUENCY RATE RATIO R CONTROL DW'DE 8 30k D 35 26 G 2 FLIP RESET 9 FLOP COINCIOENT WRITE DETECTOR MATRIX l 27DWELL START INTERVAL 3s 25 DIVIDER STOP sTART 32 FREQUENCY FREQUENCYSELECTOR SELECTOR DWFFNITEL SELECTOR FIG 3 THOMAS L. LOPOSER GORDON D.MCKINLEY INVENTORS AGENT United States Patent Office 6 (Claims. (Ql. fil-l) This application is a continuation-in-part of our prior applicationentitled, Precision Swept Oscillator, Ser. No. 481,290, filed Aug, 20,1965, now abandoned.

This invention pertains to sweep frequency oscillators or generators,and particularly to sweep frequency oscillators that provide accuratelycontrolled end frequencies for determining selected ranges andaccurately controlled rates of sweep or frequency change within theselected ranges.

Prior sweep oscillator circuits may be said to be openend circuits inwhich the values of circuit components are chosen so that the changes infrequency during sweep cycles are substantially linear between thechosen end frequencies. The accuracy retained during long periods ofoperation depends upon the stability of the components. Usually, exactlinearity is not achieved in these pcnend control circuits in whichlinearity is to be dependent upon changes in control voltage at apredetermined rate to control rate of change of frequency.

The present circuit differs from prior circuits in thatdigitahcontrolled closed-loop circuits rather than openended circuitsare utilized for controlling rates of frequency change. A closed-loopcontrol circuit of this invention utilizes output signal during sweepcycles to control the voltage applied to the voltagecontrolledoscillator at closely spaced intervals during sweep cycles. The controlcircuit includes a digital counter that functions as a frequencydivider. Usually, the oscillator signal is swept so that the rate ofchange during sweep cycles is linear, but predetermined gradualnon-linear sweep characteristics may be obtained when desired. Theaccuracy of the frequency control any time during any sweep cycle isequivalent to the frequency stability that is expected from a goodquartz crystal oscillator that is operated at room temperature.

A sweep-'requency oscillator according to this invention has manyapplications where extremely linear operation is desired. it may be usedfor laboratory tests, for spectrum analysis, or for providing localoscillator signals in search or acquisition receivers.

An object of this invention is to control accurately the frequencies ofoutput signals of sweep-frequency oscillators at all times during entiresweep cycles.

Another object is to provide in a closed control loop, a frequencydivider that is controlled by start and stop end frequency controlcircuits and rate control circuits to control sweep frequenciesaccurately.

A feature of this invention is the utilization of a digital counter as afrequency divider in an oscillator frequency control loop.

Other objects and advantages will be apparent from the specification andclaims and the accompanying drawing illustrative of the invention inwhich:

FIGURE 1 is a simplified block diagram of the invention;

3,364,437 fatentetl den. 16, 1968 FIGURE 2 is a graph to show change infrequency caused by change in divide ratio in the control loop of theoscillator of this invention; and

FTGURE 3 is a block diagram of the sweep frequency oscillator of thisinvention.

Referring to FIGURE 1, there is shown a conventional voltage controlledoscillator 11 having a feedback loop including a divider network 12, aphase comparator 14, and a reference frequency generator 16. Systemssuch as this are well known to those skilled in the art; for example,Edward M. Ulicki discussed a similar system at the 19th Annual Symposiumon Frequency Control (1965), as reported in the Proceedings for thatSyinposiurn.

The divider network 12 is basically a counter that produces an outputsignal pulse for a preset number of cycles generated at the output ofthe oscillator 11. If the oscillator ll generates a sinusoidal wave, thedivider 12 would include circuitry to square the sinusoidal shape andgenerate a pulse for each cycle of the oscillator output. The outputpulses from the divider network 12 are connected to input 13 of thephase comparator 14; the phase comparator also received a train ofpulses at its input 16 from the reference frequency generator 15. Thenumber of cycles required at the output of the oscillator 11 to producea pulse at the output of the divider network 12 is determined by adivider ratio selector 17.

The phase comparator 14 can be any one of many Well known such devices.For example, one well known phase comparator inc udes means to generatea linear ramp voltage; the ramp generator is started by a pulse from thereference frequency generator 15 and is stopped by a pulse from thedivider network 12. Thus, the magnitude of the ramp voltage isproportional to the time difference, which is also the phase difference,between the pulses generated at terminal l3 and the pulses generated atterminal 16. The ramp voltage is connected to the control circuit of theoscillator if to vary the feedback signal of the oscillator circuit.

The voltage controlled oscillator ii is a basic well known device. Itgenerates an alternating output signal the frequency of which isdependent upon a control signal, usually connected to the oscillatorfeedback loop, to change the feedback reactance. Fora given value ofcontrol voltage, the frequency of the output signal will remain constantat some predetermined value. If the control voltage, in this case fromthe phase comparator 14, is changed the output signal frequency willimmediately begin to adjust to the new value established by the newcontrol signal. The rate of frequency change is determined by the gainof the feedback loop, the gain being defined broadly as a function ofthe sampling rate (the frequency of the output signal of the frequencydivider) and the transfer functions of all circuits within the feedbackloop. If the gain is low, the change of frequency of the oscillator 11in response to change in divide ratio of divider network 12 is slow andapproaches its ultimate value asymptotically, If the gain is high, andespecially when phase delay in the feedback circuit is substantial, thecharge on the capacitor that is in the control circuit initially changesmore than is necessary to effect a required change in frequency. A curvefor frequency change therefore shows a damped oscillatory waveform foreach abrupt change of frequency. When the gain is optimum, the change infrequency is effected quickly and the desired frequency is approachedasymptotically.

The rate of change in frequency as a result of change in divide ratio isillustrated in FIGURE 2. The lowest point on the curve represents astart frequency that corresponds to an initial preselected divide ratioof a counter that is used for the divider network 12. When thepreselected divide ratio is maintained constant, the frequency of theoutput signal of the sweep frequency generator also remains constant.Under constant conditions, the time difference between the occurrence ofthe divider network 12 output pulse and the reference frequencygenerator 15 output pulse is constant. The voltage that is transferredfrom the phase comparator voltage ramp to the capacitor in the controlcircuit of the voltage controlled oscillator ll remains constant at avalue to cause the output signal of the oscillator to be equal to thefrequency of the reference signal multiplied by the number of counts ineach counting cycle of the counter of the divider network 12.

The portion 118 of the divide ratio curve of FTGURE 2 represents achange in the presetting of the divider network 12 so that a greaternumber of cycles of the output signal are counted during each countingcycle. At this point in time there exists a frequency difference betweenthe command frequency as set by the new divide ratio and the actualoutput frequency of too voltage controlled oscillator 11. The pulses atthe output of the divider network then occur at later points on thephase comparator voltage ramp. The voltage that is transferred from thevoltage ramp to the control circuit of the oscillator ill is increasedfor each successive count corresponding to the changes in frequency asrepresented by the steplike portion 19 of the frequency curve of FIG-URE 2. Each step occurs at each sampling period that corresponds to acounting cycle. As shown in FIGURE 2, the change in frequency inresponse to a change in divide ratio is greatest at the end of a firstcounting cycle when the frequency difference between the commandfrequency and the actual frequency is greatest. The changes in controlvoltage cause the frequency of the oscillator to change in the requireddirection to decrease the difference in the frequency of the output ofthe divider network i2 and the frequency of the output of the referencefrequency generator 15. The steplike changes in oscillator controlvoltage gradually become smaller as the frequency error decreases. Asdescribed above, when a desired time constant is selected for thefrequency control circuit, the desired frequency is approached asyrntotically so that the frequency control circuit is stable.

The sweep illustrated in FIGURE 2 is essentially linear. The divideratio of the divider network 12 is increased periodically to maintain anessentially constant frequency error in the loop. Usually, the number ofcounting cycles for each change in divide ratio is large so that thechange of frequency for each counting cycle is small, and the control ofthe sweep follows very accurately the programming of the counter. Thepresetting of divider network 12 is changed repeatedly during the sweepperiod while the step-like changes in control voltage are stillsubstantial. When the frequency of the oscillator ll reaches a selectedstop frequency, the divider network 12 is again preset to correspond tothe start frequency. A flyback interval is required to permit the chargeon the capacitor of the frequency control circuit to change therelatively substantial amount between the value required for the stopfrequency and the value required for the start frequency. The changes involtage on the control capacitor becomes less for successive countingcycles as illustrated by the corresponding frequency changes in aportion 29 of the frequency curve, and the frequency gradually approaches the start frequency. The interval must be long enough to ensurethat the frequency of the oscillator has been returned accurately to apredetermined start frequency before the counter is again programmed fora sweep cycle.

In accordance with the present invention, the divide ratio selector 17is replaced by a program system that controls the frequency of theoscillator 11 to sweep from some starting value to an upper limit andreturn to commence again, as shown in FIGURE 2. The block diagram ofFIGURE 3 shows a preferred system for programming the pulse traingenerated at terminal 13 of the phase comparator 14. A variable ratiofrequency divider 21 replaces the divider network 12 and the divideratio selector 17 of FIGURE 1. Again, if the oscillator 11 generates asinusoidal wave the frequency divider 21 would incorporate circuitry tosquare the sinusoidal shape and generate a pulse for each cycle of theoscillator output. The variable ratio frequency divider 21 consists ofwhat is commonly known as a ripple through counter consisting of aplurality of serially connected flip-flops. The flip-flop circuits areusually connected such that it requires a given number of input pulsesat the first ilip flop to produce one output pulse from the lastflip-flop. In the present circuit, the input pulses are the squaredwaves from the oscillator 11. By eliminating, electrically that is, someof the serially connected fliplop circuits the number of input pulsesrequired to produce an output pulse can be varied. Thus, if the input tothe first flipflop in the divider Zll is a pulse train representing thefrequency output of the oscillator 11 the output of the divider is apulse-train equal to some fraction of the input. The output pulse trainfrom the divider 21, in addition to connecting to terminal 13 of thephase comparator 14, also connects to a write gate 23 by means of a line24 and to two AND gates 28 and 29. The write gate 23 receives a binarycoded signal, assuming the system operates on a binary code, from aprogram frequency ratio control 22, and transfers the informationreceived from the ratio control to the flip-flop control terminals ofthe frequency divider 21. The program frequency ratio control 22 has twoinput channels and an output channel; one input channel connects to asweep rate divider 33 and the second input channel connects to a writegate 26. The output channel of the ratio control 22; connects to acoincident detector 35 and to the write gate 23.

The sweep rate divider 33 also has two input channels, one connected toa sweep rate selector 34 and the other connected to the AND gate 28. TheAND gate 28 has two input signals, one from the frequency divider 21, asmentioned previously, and the second from a flipfiop 3t Flip-flopcircuits normally have two ouput signals; the flip-flop 30 has oneoutput connected to the AND gate 28 and the second connected to the ANDgate 29. The output of the AND gate 29 connects to a dwell intervaldivider 31; the dwell interval divider receives a second input signalfrom a dwell time selector 32. The output of the dwell interval divider31 connects to the flip-flop 3% which also receives an input signal fromthe coincident detector 35. The coincident detector output signal alsoconnects to the input of the write gate 26 which receives informationfrom a start frequency selector 25. Finally, to complete the system, thecoincident detector 35 is connected to a stop frequency selector 36.

In operation, the start frequency selector 25 generates a binary codedsignal representing the lowest frequency which it is desired to havegenerated by the variable frequency control oscillator (VFO) Ill. Thereare any number of available circuits that can be used as a startfrequency selector; for example, a simple power source supplying a fixedvoltage to a plurality of wafer switches connected to a diode matrixwould be adequate. The wafer switches would be set to either on or offand thereby generate the desired binary code at the output of the startfrequency selector 25.

To start the VFO l1 generating the frequency curve shown in FIGURE 2 areset signal is generated on line 27. This signal closes the pluralityof gates (each gate being an AND circuit) of the write gate 25 therebytransferring the binary code generated by the frequency selector 25 tothe program frequency ratio control 22. Write gates are familiar devicesand usually are made up of a plurality of AND gates having one commoninput; in this case, the common input is the reset signal generated onthe line 27. The program frequency ratio control 22 is simply a registerconsisting of a plurality of serially connected flip-flop circuits eachhaving two stable states. Each bit in the binary code generated in thestart selector 25 presents one flip-flop in the ratio control 22. Aspresently employed, the program frequency ratio control 22 acts as astorage means for the information transferred thereto.

The information stored in the ratio control 22 is available to thecoincident detector 35, this will be discussed presently, and alsotransferred through the write gate 23 to the variable ratio frequencydivider 21. To transfer information through the write gate 23 a transferpulse must be present on the line 24. Like the write gate 26, the writegate 23 is simply a plurality of AND gates having one common input. Thevariable ratio frequency divider 22 receives the information transferredthrough the write gate 23 to preset the flip-flop circuits of theregister in the frequency divider. By presetting a. given arrangement offlip-flop circuits, the number of input pulses required from the VFO 11to produce an output pulse at terminal 13 can be either increased ordecreased. Thus, the binary code transferred from the start frequencyselector 25, through the write gate 26 to the program frequency ratiocontrol 22, through the write gate 23 to the variable ratio frequencydivider 21, determines the number of pulses, that is the number ofcycles at the output ofthe VFO 11, required to produce an output pulseat the terminal 13. The pulse train output of the frequency divider 21is compared in the phase comparator 14 for the phase difference betweenthe reference pulse train generated by the reference frequency signalgenerator 15, as explained previously. In addition, the pulse trainoutput of the frequency divider 21 pulses the write gate 23 to transferthe binary code of the program frequency ratio control 22 to thefrequency divider 21. Further the pulse train output of the frequencydivider 21 is supplied to the AND gate 28 as one input thereto.

When an AND gate has two identical input signals (commonly known as alogic ONE) it generates an output signal that is also a logic ONE. TheAND gate 28 has one input signal from the flip-flop 31) and the secondinput signal the pulse train from the frequency divider 21. Thus, so lonas the flip-flop 30 generates a logic ONE output signal to the AND gate28, the output of the gate is a pulse train identical to that generatedat the output of the frequency divider 21. The output of the AND gate 28operates the sweep rate divider 33 which is simply another registercircuit containing a plurality of serially connected flip-flops. Asexplained previously with regards to the frequency divider 21, aregister can be connected so that one output pulse is generated for agiven number of input pulses by eliminating, that is presetting, anynumber of flip-flop circuits. The sweep rate selector 34 establishes thenumber of pulses from the AND gate 28 (cycles at the output of the VFO)that are required to produce an output pulse from the rate divider 33.In its simplest form, the rate selector 34 is a power source supplying afixed voltage to a plurality of wafer switches connected to a diodematrix. By proper setting of the wafer switches the flip-flop circuitsin the rate divider 33 are preset to thus vary the number of inputpulses required to produce an output pulse.

Each pulse from the rate divider 33 changes the binary code stored inthe ratio control 22 and thereb changes the factor by which the outputfrequency of the VP0 11 is divided. At the next pulse on line 24,

the new code (dividing factor) is transferred from the ratio control 22through the write gate 23 to the frequency divider 21. The new divideratio is generated before the VFO 11 has time to establish the frequencycalled for by the previous divide ratio. As shown in FIGURE 2, the VFO11 generates four cycles before a new divide ratio is established. Thisoperation continues and the VFO 11 never levels out at a given frequencybut always increases in a substantially linear manner as shown in FIGURE2.

As mentioned previously, the binary code stored in the program frequencyratio control 22 is continuously available to the coincident detector35. Coincident detectors usually comprise a plurality of AND gates andNOR gates connected in an array. The number of AND gates and NOR gatesrequired would vary with the number of information bits in the signalsto be compared. The coincident detector 35 compares the binary code fromthe frequency control 22 with a binary signal generated by the stopfrequency selector 36 which is similar in construction and operation tothe start frequency selector 25. The binary signal from the frequencyselector 36 represents the upper frequency limit to be generated at theoutput of VFO 11, as shown in FIGURE 2.

The output of the coincident detector 35 closes the write gate 26 andagain the start frequency code from the start frequency selector 25 istransferred to the frequency ratio control 22. Transferring the startfrequency code to the ratio control 22 cancels frequency divide ratiothen existing in the ratio control. Simultaneously with the closing ofthe write gate 26, the pulse output of the coincident detector 35changes the flipflop 30 from its first stable state to its second.Immediately upon transferring the start frequency code to the programratio control 22 the output of the coincident detector 35 goes to Zerosince its two input signals are no longer identical. However, theflip-flop 39 remains in its second stable state as such devices normallyoperate in this manner. With the flip-flop St in its second stablestate, its first output, connected to the AND gate 28, goes to logicZERO and its second output, connected to the AND gate 29, changes fromlogic ZERO to logic ONE. Functionally the AND gate 29 is similar to theAND gate 28 and thus generates a logic ONE output for each pulsegenerated by the frequency divider 21. Since the AND gate 28 is now onlyreceiving the pulse train from the frequency divider 21, its output willbe a steady logic ZERO. As a result, the sweep rate divider 33 does notgenerate an output pulse to change the code, and the program frequencycontrol 22 remains at the start frequency level. This means thefrequency of the output of the VFO 11 will decrease in an attempt toreach the start frequency level. The number of cycles that are generatedby the VFO 11 before it begins to increase is determined by the dwelltime selector 32 connnected to the dwell interval divider 31.

The dwell interval divider 31 is similar to the sweep rate divider 33;it is simply a register consisting of a plurality of serially connectedfiipflop circuits. In operation, the dwell divider 31 is similar to thesweep rate divider 33. A pulse train from the variable ratio frequencydivider 21, through the AND gate 29, is connected to the dwell divider31; the number of pulses from the frequency divider (cycles at theoutput of the VFO 11) required to cause an output pulse from the dwelldivider 31 is determined by the dwell time selector 32. The dwellselector 32, like the sweep selector 34, is simply a. plurality of waferswitches connected to a power supply and to a diode matrix to preset agiven arrangement of flip-flops to thereby vary the number of inputpulses to the dwell divider 31 that are required to produce an outputpulse. Thus, if the dwell selector 32 is set at 12, it requires 12 pulsesignals from the AND gate 29 (which corresponds to twelve cycles at theoutput of the variable ratio frequency divider 21) before a signal isgenerated at the output of the dwell divider 31. At the end of the 12cycles, the dwell divider 31 generates an output pulse which changes theflip-flop 3% from its second stable state back to its first state. Againthe logic ONE output from the flip-flop 35) is connected to the AND gate28 and the signal from the flip-flop 30 the AND gate 29 would return tologic ZERO. The AND gate 28 would again pass the pulse train generatedby the variable frequency divider 2.1 and the sequence of operation isrepeated. The time during which the dwell interval divider 31 receivesthe output pulses from the variable ratio frequency divider Z1 isdefined as the flyback interval and is shown as such in FIGURE 2.

The above described operation would continuously repeat itself with thefrequency output of the VFO 11 in creasing along the line 19, of FIGURE2, the divide ratio, that is the factor by which the VFO output isdivided, increasing along the curve 18. When the frequency eaches itsupper limit, the flyback interval is initiated during which time theoutput frequency reduces to its starting point as shown by the curve 2t)of FIGURE 2.

It is not deemed necessary, as recognized by one skilled in the art oflogic circuit design, to completely describe each of the many circuitsused in the various components shown in FIGURES 1 and 3. Each of thevarious components is thoroughly described in many excellent texts; forexample, reference is made to the text entitled Digital ComputerComponents and the Circuits by R. K. Richards, published by VanNostrand.

While only one embodiment of the invention has been described in detailherein and shown in the accompanying drawing, it will be evident thatvarious modifications are possible in arrangement and construction ofits components without departing from the scope of the invention.

We claim:

l. A frequency-controlled oscillator having an input control circuit forcontrolling the frequency of the signal at the output of saidoscillator,

a counter having an input connected to the output of saidfrequency-controlled oscillator for counting the cycles of the outputsignal of said oscillator, means operating in response to said counterreaching a predetermined end count to reset said counter,

control means connected between the output of said counter and saidinput control circuit of said oscillator, said control means operatingin response to application of signal from said counter to controlaccurately the frequency of said oscillator as a predetermined ratio ofthe frequency of the output signal of said counter, said counterapplying a cycle of signal to said control means in response to itsreaching a final count during each of its counting cycles,

presetting means connected to said counter for determining the number ofcounts in each of said counting cycles, and

rate control means operating in cooperation with said presetting meansto control the rate of change of the number of counts in successive onesof said counting cycles, thereby, to control accurately the rate ofchange of frequency during sweep cycles of said sweep frequencyoscillator.

2. A sweep oscillator having a variable-frequency voltage-controlledoscillator, a phase comparator, and a countsaid counter having an inputconnected to the output of said variable-frequency voltage-controlledoscillator to count the successive cycles of the output signal of saidcontrolled oscillator,

a reference frequency signal generator,

said comparator having one input connected to said reference frequencysignal generator and another input connected to an output of saidcounter, the output of said comparator being connected to saidvariablefrequency voltage-controlled oscillator, said counter respondingcyclically to application of output signal S from said controlledoscillator to produce a signal for the final count of each of itscounting cycles, means for presetting said counter to determine thenumber of counts in each of said counting cycles, the output frequencyof said sweep oscillator being the frequency of the signal applied tosaid comparator from said reference frequency signal generatormultiplied by said predetermined number of counts during a countingcycle, and

means for changing a predetermined rate the number of counts insuccessive ones of said counting cycles to control accurately the changein frequency of the output of said sweep oscillator during eachsuccessive sweeping cycle of said oscillator as controlled by eachsuccessive counting cycle of said counter.

A sweep frequency oscillator having precisely controlled frequenciesover a sweep range comprising:

a variable-frequency voltage-controlled oscillator circuit of the typethat has a voltage-controlled oscillater and a phase comparator, saidphase comparator responding to application of signal derived from saidoscillator to control the frequency of the output signal of saidoscillator circuit so that it is equal to a selected harmonic frequencyof said reference signal,

said oscillator circuit having a sub-harmonic counter connected betweenthe output of said variablefrequeucy oscillator and said phasecomparator to apply to said phase comparator said signal derived fromsaid oscillator, said counter functioning as a variable-ratio frequencydivider, said sub-harmonic counter providing an output signal at the endof each of its counting cycles to form a sub-harmonic signal that has afrequency that is equal to the frequency of said output signal of saidoscillator divided by the number of counts that are made during eachcycle of operation of said counter, said counter having presettingcircuits for controlling the number of counts during each of itscounting cycles,

a write matrix having a write-signal input connected to receive saidoutput signal of said sub-harmonic counter, a presetting digital outputconnected to said presetting circuits of said sub-harmonic counter, anda program input for determining said presetting digital output, saidwrite matrix being responsive to application of said output signal ofsaid sub harmonic counter to preset said counter according to programinformation supplied to said input,

a rate selector frequency divider connected to said counter to receivesaid output signal at the end of each of its counting cycles, said rateselector frequency divider having an output connected to said programinput circuits of said write matrix, means for controlling said dividerto select the ratio of the frequency of its input to the frequency ofits output, and

the rate of counting of said sub-harmonic counter during each of itscycles bein controlled by the selected ratio of said divider during eachof said cycles, whereby, said rate selector frequency divider determinesthe rate of counting of said sub-harmonic counter and thereby closelycontrols the rate of frequency change during each sweep cycle of saidsweep frequency oscillator.

4, A sweep frequency oscillator including a variablefrequencyvoltage-controlled oscillator circuit of the type that has avoltage-controlled oscillator and phase cornparator, said phasecomparator responding to application of signal derived from saidvoltage-controlled oscillator and a reference signal to control thefrequency of the output signal of said oscillator circuit so that it isequal to a selected harmonic frequency of said reference signal,

a counter connected between the output of said variable-frequencyoscillator and said phase comparator, said counter functioning as avariable-ratio frequency divider, said counter providing an outputsignal at the end of each of its counting cycles to form a sub-harmonicsignal of said oscillator divided by the number of counts that are madeduring each cycle of operation of said counter, the frequency of saidoscillator being controlled by said comparator so that the frequency ofsaid sub-harmonic signal is equal to the frequency of said referencesignal,

counter control circuits connected to said counter,

start frequency selector means responsive to a resetting signal formomentarily applying presetting information to said counter controlcircuits at the start of each counting cycle for determining the startfrequency of the output signal of said sweep frequency oscillator,

rate selector control means connected to said counter control circuitsto determine the rate of change of count for successive cycles ofoperation of said counter, thereby, to determine the rate of frequencychange of said output signal of said sweep frequency oscillator, and

stop frequency control means connected to said counter control circuitsand to said start frequency selector means, said stop frequency controlmeans operating in response to said counter reaching a predeterminedcount that corresponds to the lowest frequency of the selected sweeprange to apply said resetting signal to said start frequency selectormeans to restart the sweeping cycle of said sweep frequency oscillator.

5. A sweep frequency oscillator having precisely controlled selectableend frequencies and closely spaced controlled frequencies over a sweeprange terminated by the end frequencies comprising:

a variable-frequency voltage-controlled oscillator circuit of the typethat has a voltage controlled oscillator and phase comparator, saidphase comparator responding to application of signal derived from saidoscillator and a reference signal to control the he quency of the outputsignal of said oscillator circuit so that it is equal to a selectedharmonic frequency of said reference signal,

said oscillator circuit having a counter connected between the output ofsaid variable-frequency oscillator and said comparator to apply to saidphase comparator said signal derived from said oscillator, said counteroperating as a digital variable-ratio frequency divider,

a write matrix having a write signal input connected to receive saidoutput signal of said counter, a presetting digital output connected tosaid presetting circuits of said counter, and a program input fordetermining said presetting digital output, said write matrix beingresponsive to application of said out put signal of said oscillator topreset said counter according to program information applied to saidprogram input,

rate selector control means connected to said program input of saidwrite matrix, said rate selector control means operable during a sweepperiod of said sweep frequency oscillator to change the count of saidcounter during its successive counting cycles, thereby to controlaccurately the rate of change of frequency of said sweep frequencyoscillator,

stop frequency control means operating in response to said write matrixpresetting said counter to a pre determined final end count to provide astart resetting signal, thereby to determine the final end frequency ofsuccessive sweep cycles of said sweep frequency oscillator,

start frequency selector means, start control means operable formomentarily connecting said start frequency selector means to saidprogram input of said write matrix, said start control means having acontrol circuit connected to said stop frequency control means toreceive said start resetting signal, and said start control meansoperating in response to operation of said stop frequency control meansto determine the number of counts in a counting cycle at the beginningof each of said sweep cycles, thereby to control accurately the startfrequency of said sweep cycles.

6. A sweep frequency oscillator having precisely controlled selectableend frequencies and closely spaced controlled frequencies over a sweeprange terminated by the end frequencies comprising:

a variable-frequency voltage-controlled oscillator circuit of the typethat has a voltage controlled oscillator and a phase comparator, saidphase comparator responding to application of signal derived from saidoscillator and a reference signal tocontrol the frequency of the outputsignal of said oscillator circuit so that it is equal to a selectedharmonic frequency of said reference signal,

said oscillator circuit having a counter connected between the output ofsaid variablefrequency oscillator and said comparator to apply to saidphase comparator said signal derived from said oscillator, said counteroperating as a digital variable-ratio frequency divider,

write matrix having a write signal input connected to receive saidoutput signal of said counter, a presetting digital output connected tosaid presetting circuits of said counter, and a program input fordetermining said presetting digital output, and write matrix beingresponsive to application of said output signal of said oscillator topreset said counter according to program information applied to saidprogram input,

program counting control circuit connected to said program input of saidwrite matrix for transferring presetting information to said counter,

a start-frequency selector, a sweep-rate control circuit,

and a stop-frequency selector,

write control means for connecting said start-frequency said sweep-ratecontrol circuit including a sweep-rate selector circuit, a dwell timeselector circuit, and a switching circuit, said sub-harmonic counterbeing connected to said switching circuit to apply said output signal atthe end of each of its counting cycles to said switching circuit, saidswitching circuit also being connected to said coincidence control meansto receive an operating pulse in response to said program countingcontrol circuit reaching each of said final end counts, said switchingcircuit being connected to said dwell time selector circuit and to saidsweep-rate selector circuit, said switching circuit operating inresponse to the application of said operating pulse to apply said outputsignal of said sub-harmonic counter to said dwell time selector circuit,said dwell time selector circuit operating in response to reception of apreselected number of pulses of said output signal to operate saidswitching circuit to remove said output signal of said subharmoniccounter from said dwell time selector circuit and to apply said outputsignal to said sweeprate selector circuit, said sweep rate selectorcircuit being connected to said program counting control lll circuit,said sweep-rate selector circuit operating in response to application ofsaid output signal to divide the repetition rate of said output signalby a preselected number that has been set into said sweeprate selectorcircuit and applying the divided signal to said program counting controlcircuit, said pro gram counting control circuit responding toapplication of said divided signal to advance the count of said presetdigital output of said program counting control circuit that is appliedto said sub-hat-- monic counter and to apply a count to said coincidencemeans until said end count is reached, whereby the end frequencies ofsaid sweep range are determined by the settings of said start-frequencyselector and said stop-frequency selector respectively and the rate ofsweep within said sweep range is accurately controlled by operation ofsaid sweep rate control circuit.

No references cited.

IGHN KOMINSKI, Primary Examiner.

1. A FREQUENCY-CONTROLLED OSCILLATOR HAVING AN INPUT CONTROL CIRCUIT FORCONTROLLING THE FREQUENCY OF THE SIGNAL AT THE OUTPUT OF SAIDOSCILLATOR, A COUNTER HAVING AN INPUT CONNECTED TO THE OUTPUT OF SAIDFREQUENCY-CONTROLLED OSCILLATOR FOR COUNTING THE CYCLES OF THE OUTPUTSIGNAL OF SAID OSCILLATOR, MEANS OPERATING IN RESPONSE TO SAID COUNTERREACHING A PREDETERMINED END COUNT TO RESET SAID COUNTER, CONTROL MEANSCONNECTED BETWEEN THE OUTPUT OF SAID COUNTER AND SAID INPUT CONTROLCIRCUIT OF SAID OSCILLATOR, SAID CONTROL MEANS OPERATING IN RESPONSE TOAPPLICATION OF SIGNAL FROM SAID COUNTER TO CONTROL ACCURATELY THEFREQUENCY OF SAID OSCILLATOR AS A PREDETERMINED RATIO OF THE FREQUENCYOF THE OUTPUT SIGNAL OF SAID COUNTER, SAID COUNTER APPLYING A CYCLE OFSIGNAL TO SAID CONTROL MEANS IN RESPONSE TO ITS REACHING A FINAL COUNTDURING EACH OF ITS COUNTING CYCLES, PRESETTING MEANS CONNECTED TO SAIDCOUNTER FOR DETERMINING THE NUMBER OF COUNTS IN EACH OF SAID COUNTINGCYCLES, AND RATE CONTROL MEANS OPERATING IN COOPERATION WITH SAIDPRESETTING MEANS TO CONTROL THE RATE OF CHANGE OF THE NUMBER OF COUNTSIN SUCCESSIVE ONES OF SAID COUNTING